1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device including therein MIS (Metal Insulator Semiconductor) transistors and a method for manufacturing the same.
2. Description of the Related Art
Semiconductor memory devices such as a DRAM (Dynamic Random Access Memory) device incorporate therein capacitors as storage elements and MOS (Metal Oxide Semiconductor) transistors for driving the capacitors. Reduction in the design rule of the semiconductor memory devices has recently been accelerated, which reduces the device area occupied by the MOS transistors, with the result that a sufficient gate width is difficult to secure. The reduction in the gate width causes a decrease in the ON-current of the MOS transistors, thereby inducing a reduction in the S/N ratio of the DRAM device.
There is known a vertical-type MOS transistor as a MIS transistor capable of securing a larger gate width with a smaller occupied area, in which source and drain regions and gate electrodes are arranged in a three-dimensional structure. To form the vertical-type MOS transistor, however,  additional processes must be performed of obtain the three-dimensional structure, and thus the number of the processes increases considerably as compared with the planar-type MOS transistor. In such circumstances, there is an increasing demand for a semiconductor memory device that achieves a low fabrication cost in forming the planar-type MOS transistor, while securing a sufficient gate width without an increase in the number of processes.
Patent Publication JP-2001-035913A describes a planar-type MOS transistor, such as shown in FIG. 11 of the accompanying drawings. The process for forming the planar-type MOS transistor includes the steps of forming element-isolating region 10B on a silicon substrate 11, known as a STI (Shallow Trench Isolation) structure, and removing the surface portion of the isolation oxide film 13 embedded in the trench 12 of the element-isolation region 10B. The removal of the surface portion of the isolation oxide film 13 generates a step difference between the top surface of the silicon substrate 11 configuring the element-forming regions 10A and the surface of the isolation oxide film 13 in the element-isolation region 10B.
In JP-2001-035913A, the formation of the step difference between the top surface of the silicon substrate 11, i.e., the element-forming regions 10A and the top surface of the isolation oxide film 13 in the element-isolation region 10B prolongs the length of the surface area of the silicon surface at the location of the step difference, which results in an increase of the gate width denoted by “W” in FIG. 11.
In the method described in JP-2001-035913A; however, a corner edge 43 may be formed on the edge of the surface region of the silicon substrate 11 in the element-forming regions 10A, as shown in FIG. 11. The corner edge 43 may cause a concentration of electric field onto a portion of the gate oxide film 14 during dry etching of a conductor film to form the gate electrodes 15. The concentration of the electric field may etch the gate oxide film 14 in an excessive amount to reduce the thickness of the gate oxide film 14. A smaller thickness of the gate oxide film 14 causes a smaller withstand voltage thereof, to degrade the reliability of the MOS transistor.